1. Field of the Invention
The present invention relates to a receiving circuit provided with an active filter for filtering and outputting an inputted transmission signal by a predetermined frequency characteristic, and a frequency characteristic adjusting circuit for adjusting the frequency characteristic of the active filter and performing multi-slot receiving, a transceiver circuit provided with the receiving circuit and a transmitting circuit, and a communication apparatus provided with the transceiver circuit.
2. Description of the Related Art
In the case where an active filter is incorporated in an integrated circuit (referred to as an IC hereinafter), there is such a case that the IC cannot obtain an expected frequency characteristic due to variation in elements such as a resistor, a capacitor, and a transistor upon manufacturing ICs. Therefore, most ICs in the case of incorporating an active filter include a frequency characteristic adjusting circuit for adjusting frequency characteristic. In this case, the frequency characteristic means the center frequency in a band pass filter (BPF) and a cut-off frequency in a high pass filter (HPF) or a low pass filter (LPF), respectively. In addition, the active filter means a filter manufactured by combining active elements such as an operational amplifier and a transistor with a configuration including a resistor, a capacitor, a coil and the like.
FIG. 13 is a timing chart showing an operation at the time of power source ON of an active filter incorporated in an IC, in a receiver circuit according to a prior art. The active filter starts to operate at a power source ON timing of a power source ON/power source OFF signal to the active filter, and frequency characteristic of the active filter is adjusted by a frequency characteristic adjusting circuit. An adjusting time Δt is required until the frequency characteristic of the active filter is adjusted to a desired frequency f0, and during this time, any data cannot be received. Although an example method for adjusting the frequency characteristic of the active filter is disclosed in Japanese patent laid-open publication No. JP-2002-94357-A, there is such a problem that it often needs a comparatively long time for adjustment for the frequency characteristic.
FIG. 14 is a schematic diagram showing an up frame configuration and a detail frame configuration of one receiving slot, in a personal handy-phone system (referred to as a PHS system hereinafter) according to a prior art.
In (a) of FIG. 14, an up frame from a terminal unit to a base station of the PHS system is constituted by including four transmitting slots TS1, TS2, TS3, and TS4 and four receiving slots RS1, RS2, RS3, and RS4. In (b) of FIG. 14, one receiving slot RS1 is constituted by including a Ramp time for transient response R (4 bits), a start symbol SS (2 bits), a preamble PR (6 bits), a synchronous word UW (16 bits), a channel type CI (4 bits), a slow associated control channel (SACCH) SA (16 bits) which is a control channel, a traffic channel TCH (160 bits), and a guard bit GB (18 bits).
FIG. 15 is a timing chart showing a relationship among a receiving slot, a power source control signal for a receiver circuit, and a receiving signal strength indicator (RSSI) voltage in multi-slot receiving of a receiver circuit for the PHS system according to the prior art. In this case, the multi-slot receiving is such a case that data receiving is performed using a plurality of bits as shown in FIG. 14, and FIG. 15 shows that data receiving is performed using four slots continuously.
The RSSI voltage is provided for showing a field strength of a desired wave received by an antenna by detecting a transmission signal level in an intermediate frequency amplifying circuit of a radio receiver circuit, for example, and the voltage is used for carrier sense, for example. The RSSI voltage is configured so as to output a DC voltage corresponding to an amplitude of an inputted radio frequency signal (referred to as an RF signal hereinafter), and an outputted DC voltage also becomes large when a signal level of the inputted RF signal is large. Therefore, upon performing carrier sense, when the RSSI voltage has a high level, it is judged that radio frequency thereof is used. In the present specification, a binary signal level is represented by a high level (or H level) and a low level (or L level).
The carrier sense is performed between the receiving slots in order to determine whether or not the next receiving slot is available. However, when the RSSI voltage at the previous slot is maintained to have the high level, the radio frequency is erroneously judged as being used and data cannot be received. Therefore, the field strength of the next slot needs to be detected after the RSSI voltage once falls to the low level. In order to lower the RSSI voltage to the low level, such an operation is required that the power source is turned OFF once between the receiving slots, and then is turned ON again to monitor the RSSI voltage. Between the slots, there is a no-signal time interval which is referred to as a guard bit GB, and a transient response due to power source ON/OFF needs to be ended during the time interval. In the case of the PHS system, the time interval of the guard bit GB is 41.7 μsec, and it is necessary that the power source is turned OFF within the time interval to lower the RSSI voltage into the low level, and then, the power source is turned ON again to receive the next slot.
FIG. 16 is a block diagram showing a receiver circuit 30C according to a prior art. Referring to FIG. 16, the receiver circuit 30C is constituted by including a front-end circuit 2, an active filter circuit 3 including an active filter 4 and a frequency characteristic adjusting circuit 5, a demodulator 6, and a power source ON/OFF control terminal 29.
An inputted RF signal is inputted to the front-end circuit 2, and the front-end circuit 2 low-noise amplifies the inputted RF signal, performs frequency conversion to a predetermined intermediate frequency signal, and then, outputs the same signal to the active filter 4 of the active filter circuit 3. In this case, the active filter circuit 3 is constituted by including the active filter 4 and the frequency characteristic adjusting circuit 5, and the frequency characteristic of the active filter 4 is adjusted by the frequency characteristic adjusting circuit 5. The RF signal inputted to the active filter circuit 3 is subject to band limitation according to the above-mentioned adjusted frequency characteristic and is outputted to the demodulator 6. In this case, a power source ON/OFF control terminal 29 is connected to the front-end circuit 2, the active filter circuit 3, and the demodulator 6, and the frequency adjustment operation of the active filter circuit 3 starts in response to a power source ON signal of the power source control signal S29 inputted via the power source ON/OFF control terminal 29.
However, in the configuration of the receiver circuit according to the above-mentioned prior art, since the power source of the active filter circuit 3 performs ON/OFF operation between slots at multi-slot receiving, there is such a problem that adjustment of the frequency characteristic starts at a timing of the power source ON signal and adjustment operation is not ended within the guard bit GB.
FIG. 17 is a timing chart showing a transient response operation at the multi-slot receiving of the receiver circuit 30C shown in FIG. 16. As is apparent from FIG. 17, FIG. 17 shows that any frequency adjustment of the active filter 4 is not ended within the guard bit GB.